1. Field of the Invention
This invention relates to circuits and methods for reducing write disturb in non-volatile memory and particularly reducing write disturb in non-volatile analog and multilevel memory.
2. Description of Related Art
Non-volatile semiconductor memories such as EPROM, EEPROM, and Flash memories are well known. In such memories, a threshold voltage of a memory cell indicates a data value stored in the memory cell. When writing to a selected memory cell in a conventional non-volatile memory array, programming voltages are applied via a word-line connected to a control gate of the selected cell, a bit-line connected to a drain of the selected cell, and a source-line coupled to a source of the selected cell. The combination of programming voltages changes the threshold voltage of the selected cell typically by causing Fowler-Nordheim (F-N) tunnelling or channel hot electron (CHE) injection which charges (or discharges) a floating gate in the selected memory cell. For example, to induce CHE injection in a selected memory cell containing a typical N-channel floating gate transistor, the word-line voltage for the selected cell is raised to about 12 volts or higher; the bit-line voltage for the selected cell is raised to about 6 volts or higher; and a source-line for the array is grounded.
During a write to a selected memory cell, the high bit-line and word-line voltages for the selected memory call can create large voltage differences between the floating gate and drain or control gate of unselected memory cells and thereby induce Fowler-Nordheim tunneling that disturbs threshold voltages of these unselected memory cells. The voltage difference between the drain and floating gate of an unselected memory cell subjects the memory cell to a disturb referred to herein as drain disturb. The voltage difference between the control gate and the floating gate of an unselected memory cell subjects the memory cell to a disturb referred to herein as gate disturb. Typically, drain disturb is more severe than gate disturb because the magnitude of the electric field in a tunnel layer between the floating gate and the drain is greater than the electric field in an interpoly dielectric layer between the floating gate and the control gate and because, theoretically, the tunneling current density I that disturbs a threshold voltage depends exponentially on an electric field E as indicated in equation 1.
Equation 1: EQU I=A*E.sup.2 *e.sup.-B/E
where A and B depend on memory cell structure.
The disturbance of threshold voltages can accumulate through repeated programming of memory cells in the same column or row and change the data values stored in unselected cells. Depending on the memory, a data value stored in a memory cell may be binary (a bit 0 or 1), multi-level (a value from a set of discrete values), or analog (a value within a continuous range of possible values). For binary memories, the accumulated disturbance of a threshold voltage must be relatively large (on the order of a volt or more) to change the threshold voltage from a state indicating a first binary value to a state indicating the second binary value. For a multi-level or analog memory, distinguishable threshold voltages for data values can differ by a few millivolts, and small disturbances of threshold voltages limit the threshold voltage resolution in the memory. Accordingly, methods and circuits that reduce disturbance of threshold voltages in multi-level and analog non-volatile memories are sought.
One way to reduce threshold voltage disturb is to reduce bit-line and word-line lengths by arranging memory cells in several small arrays rather than one large array. With small arrays, fewer memory cells are on the same row or column so that programming a selected memory cell disturbs fewer unselected memory cells; and the accumulated programming disturb for each memory cell is less. For example, dividing a large array into four small arrays can divide bit-line and word-line lengths in half and reduce accumulation of threshold voltage disturbance in half. However, four small arrays have about twice the overhead in decoding circuitry as does one large array containing the same number of memory cells. Methods and circuits that reduce disturbance of threshold voltages and have low overhead costs are still needed.